1. Field of the Invention
This invention relates to generating frequency signals in a signal processing system.
2. Description of the Related Art
Phase-Locked Loop (PLL) circuits have been used in many wireline and wireless applications for generating carrier frequencies and timing reference signals.
FIG. 1(a) shows a PLL which is commonly used in a communications transceiver. This circuit includes a phase and frequency detector 1, a loop filter 2, and a voltage-controlled oscillator 3 which outputs a signal fout at a desired frequency. A feedback loop connecting the oscillator to an input of the phase and frequency detector includes a divider 4 which divides the output of the oscillator by a value of (N+1)/N. A modulus control circuit outputs a signal to the divider for controlling the value of N.
In a PLL of the aforementioned type, it is well known that a trade-off exists between loop bandwidth and channel spacing. It is also known that channel spacing is the same as the comparison frequency. Given this relationship, it is often desirable to set the loop bandwidth of the PLL to be smaller than the comparison frequency by a factor often. Reducing the loop bandwidth to this value, however, produces a number of drawbacks.
For example, loop bandwidth not only affects channel spacing, it also affects the lock time and amount of phase noise in a PLL. In fact, loop bandwidth is inversely proportional to both of these values. Therefore, reducing the loop bandwidth to a value smaller than the comparison frequency by a factor of ten will produce a commensurate increase in phase noise and lock time, which has found to be undesirable for many applications.
Another drawback of the aforementioned PLL relates to a second type of noise. This noise appears in the form of spurious signals generated from mismatches that occur, for example, from the charge pump and the phase and frequency detector. More specifically, as shown in FIG. 1(b), one mismatch occurs between the UP and DOWN current (or more accurately the current sources) of the charge pump. Another mismatch occurs between the UP and DOWN signal paths in the phase and frequency detector, where ideally no mismatch should exist. These mismatches generate spurious signals which propagate throughout the host system to degrade performance and therefore, like phase noise, are also considered to be undesirable.
FIG. 2 shows the manner in which these spurious signals are formed. In this diagram, fout corresponds to the output frequency of the phase-locked loop and fcutoff corresponds to the cutoff frequency of the PLL loop filter. The difference between fout and fcutoff defines the loop bandwidth of the circuit. In operation, mismatches along the signal path of the loop generate one or more spurious signals fsp that are located very close to the output frequency fout. In fact, the spurious signals are so close to the output frequency (Δf is very small) that they lie within the loop bandwidth of the circuit and therefore cannot be removed by the loop filter. These unsuppressed spurious signals further contribute to the degradation of signal quality and performance of the host system.
In view of the foregoing discussion, it is evident that there is a need for a system and method for effectively suppressing noise in phase-locked loop circuits and especially loop circuits that are used in host systems having low noise and lock-time requirements.